 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator ISL8088 The ISL8088 is a high efficiency, dual synchronous step-down DC/DC regulator that can deliver up to 800mA continuous output current per channel. The supply voltage range of 2.75V to 5.5V allows the use of a single Li+ cell, three NiMH cells or a regulated 5V input. The current mode control architecture enables very low duty cycle operation at high frequency with fast transient response and excellent loop stability. The ISL8088 operates at 2.25MHz switching frequency allowing the use of small, low cost inductors and capacitors. Each channel is optimized for generating an output voltage as low as 0.6V. The ISL8088 has a user configurable mode of operation-forced PWM mode and PFM/PWM mode. The forced PWM mode operation reduces noise and RF interference while the PFM mode operation provides high efficiency by reducing switching losses at light loads. In PFM mode of operation, both channels draw a total quiescent current of only 30A hence enabling high light load efficiency in order to maximize battery life. The ISL8088 offers a 1ms Power-Good (PG) to monitor both output at power-up. When shutdown, ISL8088 discharges the outputs capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL8088 is offered in a 3mmx3mm 10 Ld DFN package with 1mm maximum height. The complete converter occupies less than 1.8cm2 area. ISL8088 Features * Internal Current Mode Compensation * 100% Maximum Duty Cycle for Lowest Dropout * Selectable Forced PWM Mode and PFM Mode * External Synchronization up to 4MHz * Start-up with Pre-biased Output * Soft-Stop Output Discharge During Disabled * Internal Digital Soft-Start - 2ms * Power-Good (PG) Output with 1ms Delay Applications*(see page 17) * DC/DC POL Modules * C/P, FPGA and DSP Power * Plug-in DC/DC Modules for Routers and Switchers * Test and Measurement Systems * Li-ion Battery Power Devices * Bar Code Readers Efficiency Characteristics Curve 100 90 EFFICIENCY (%) 80 70 60 50 40 0.0 1.8VOUT-PWM VIN = 5V 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 1.8VOUT-PFM 2.5VOUT-PWM 2.5VOUT-PFM April 29, 2010 FN6858.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8088 Typical Application L1 2.2H LX1 C2 10F PGND INPUT 2.75V TO 5.5V VIN C1 10F EN1 ISL8088 EN2 LX2 PG PGND C4 10F R5 200k L2 2.2H R2 316k OUTPUT1 2.5V/800mA C3 10pF FB1 R3 100k OUTPUT2 1.8V/800mA C5 10pF SYNC FB2 R6 100k PGND 2 FN6858.1 April 29, 2010 ISL8088 Pin Configuration ISL8088 (10 LD 3X3 DFN) TOP VIEW FB1 EN1 VIN LX1 NC 1 2 3 4 5 PD 10 FB2 9 8 7 6 EN2 PG LX2 SYNC Pin Descriptions DFN SYMBOL 1 FB1 DESCRIPTION The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1 regulator output voltage. Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge output capacitor when driven to low. Do not leave this pin floating. Input supply voltage. Connect 10F ceramic capacitor to power ground. Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1. Recommended to connect this pin to the exposed pad. Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode. Connect to an external function generator for Synchronization, and negative edge trigger. Do not leave this pin floating. Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2. 1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the VOUT1 and VOUT2 voltages. There is an internal 1M pull-up resistor. Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge output capacitor when driven to low. Do not leave this pin floating. The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any voltage between the power-rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage. The exposed pad must be connected to PGND for proper electrical performance. Add as much vias as possible for optimal thermal performance. 2 3 4 5 6 EN1 VIN LX1 NC SYNC 7 8 9 10 LX2 PG EN2 FB2 - PD Ordering Information PART NUMBER (Notes 2, 3) ISL8088IRZ ISL8088IRZ-T (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8088. For more information on MSL please see techbrief TB363. PART MARKING 8088 8088 TEMP. RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG. DWG. # L10.3x3C L10.3x3C 3 FN6858.1 April 29, 2010 ISL8088 Absolute Maximum Ratings (Reference to GND) Supply Voltage (VIN) VIN . . . . . . . . . . . EN1, EN2, PG, SYNC . LX1, LX2 . . . . . . . . LX1, LX2 . . . . . . . . . .............. FB1, FB2 . . . . . . . . . ESD Rating Human Body Model Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V . . . . -0.3V to 7V (20ms) . . . . -0.3V to VIN + 0.3V . . . . . . . . -1.5V to 6.5V . . . . . . . . -1.5V (100ns) -0.3V (DC) to 7V (20ms) . . . . . . . . -0.3V to 2.7V Thermal Information Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld 3x3 DFN Package (Notes 4, 5) 49 4 Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN Supply Voltage Range . . . . . Load Current Range Per Channel. Ambient Temperature Range . . . Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75V to 5.5V . . 0mA to 800mA . -40C to +85C -40C to +125C . . . . . . . . . . . . . . . . . . . . . . . . . 3kV . . . . . . . . . . . . . . . . . . . . . . . . 300V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions: TA = -40C to +85C, VIN = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 2.2H, C1 = 10F, C2 = C4 = 10F, IOUT1 = IOUT2 = 0A to 800mA. (Typical values are at TA = +25C, VIN = 3.6V). Boldface limits apply over the operating temperature range, -40C to +85C. SYMBOL TEST CONDITIONS MIN MAX (Note 6) TYP (Note 6) UNITS PARAMETER INPUT SUPPLY VIN Undervoltage Lockout Threshold Quiescent Supply Current VUVLO IVIN Rising Falling SYNC = VIN, EN1 = EN2 = VIN, no load at the output and no switches switching. VFB1 = VFB2 = 0.7V SYNC = GND, EN1 = EN2 = VIN, FS = 2.25MHz, no load at the output 2.1 2.5 2.4 30 2.75 V V 50 A 0.1 6.5 1 12 mA A Shut Down Supply Current OUTPUT REGULATION FB1, FB2 Regulation Voltage FB1, FB2 Bias Current Line Regulation Soft-Start Ramp Time Cycle OVERCURRENT PROTECTION Peak Overcurrent Limit ISD VFB_ IFB_ VIN = 5.5V, EN1 = EN2 = GND 0.590 VFB = 0.55V VIN = VO + 0.5V to 5.5V (minimal 2.75V, IOUT = 0A) 0.6 0.1 0.2 2 0.610 V A %/V ms Ipk1 Ipk2 Iskip1 Iskip2 VIN = 3.6V 0.95 0.95 180 180 1.2 1.2 250 250 1.6 1.6 360 360 A A mA mA Peak SKIP Limit LX1, LX2 P-Channel MOSFET ON-Resistance VIN = 5.5V, IO = 200mA VIN = 2.75V, IO = 200mA 180 320 350 450 m m 4 FN6858.1 April 29, 2010 ISL8088 Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions: TA = -40C to +85C, VIN = 2.75V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 2.2H, C1 = 10F, C2 = C4 = 10F, IOUT1 = IOUT2 = 0A to 800mA. (Typical values are at TA = +25C, VIN = 3.6V). Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) SYMBOL TEST CONDITIONS VIN = 5.5V, IO = 200mA VIN = 2.75V, IO = 200mA LX_ Maximum Duty Cycle PWM Switching Frequency Synchronization Range LX Minimum On-Time Soft Discharge Resistance PG Output Low Voltage PG Pull-up Resistor Internal PGOOD Low Rising Threshold Internal PGOOD Low Falling Threshold Delay Time (Rising Edge) Internal PGOOD Delay Time (Falling Edge) EN1, EN2, SYNC Logic Input Low Logic Input High SYNC Logic Input Leakage Current Enable Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. ISYNC IEN_ Pulled up to 5.5V 1.4 0.1 0.1 150 25 1 1 0.4 V V A A C C Percentage of nominal regulation voltage Percentage of nominal regulation voltage 88 82 Sinking 1mA, VFB = 0.5V 1 92 89 1 1 2 96 91 0.3 V M % % ms s RDIS_ SYNC = 0 (forced PWM mode) EN = LOW 80 100 FS 1.8 2.7 MIN MAX (Note 6) TYP (Note 6) UNITS 180 320 100 2.25 2.7 4 100 130 350 450 m m % MHz MHz ns PARAMETER N-Channel MOSFET ON-Resistance 5 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. 100 90 EFFICIENCY (%) 80 70 60 50 40 0.0 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 Typical Operating Performance 100 90 EFFICIENCY (%) 2.5VOUT - PWM 1.5VOUT - PWM 1.2VOUT - PWM 1.8VOUT - PWM 80 70 60 50 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT LOAD (A) 0.7 0.8 2.5VOUT - PFM 1.2VOUT - PFM 1.8VOUT - PFM 1.5VOUT - PFM FIGURE 1. EFFICIENCY vs LOAD 2.25MHz 3.3VIN PWM FIGURE 2. EFFICIENCY vs LOAD 2.25MHz 3.3VIN PFM 100 90 EFFICIENCY (%) 80 70 60 50 40 2.5VOUT - PWM 3.3VOUT - PWM 1.5VOUT - PWM 1.8VOUT - PWM 100 90 80 70 60 50 40 0.0 EFFICIENCY (%) 1.5VOUT - PFM 1.2VOUT - PFM 3.3VOUT - PFM 1.2VOUT - PWM 1.8VOUT - PFM 2.5VOUT - PFM 0.0 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT LOAD (A) FIGURE 3. EFFICIENCY vs LOAD 2.25MHz 5VIN PWM FIGURE 4. EFFICIENCY vs LOAD 2.25MHz 5VIN PFM 0.30 POWER DISSIPATION (W) OUTPUT VOLTAGE (V) 0.25 3.3VIN - PWM MODE 0.20 0.15 0.10 0.05 0.00 0.0 3.3VIN - PFM 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 5VIN - PWM MODE 1.23 1.22 1.21 1.20 1.19 1.18 1.17 0.0 3.3V VIN PWM 3.3V VIN PFM 5VIN PFM MODE 5VIN PWM MODE 5VIN - PFM MODE 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT LOAD (A) 0.7 0.8 FIGURE 5. POWER DISSIPATION vs LOAD 2.25MHz 1.8VOUT PWM FIGURE 6. VOUT REGULATION vs LOAD 2.25MHz 1.2VOUT PFM 6 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 1.56 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.55 1.54 1.53 1.52 1.51 1.50 0.0 3.3V VIN PWM 5VIN PWM MODE 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 5 VIN PFM MODE 3.3V VIN PFM 1.84 1.83 1.82 1.81 1.80 1.79 1.78 0.0 3.3V VIN PWM 0.1 0.2 0.3 0.4 0.5 OUTPUT LOAD (A) 0.6 0.7 0.8 5 VIN PFM MODE 3.3V VIN PFM 5VIN PWM MODE Typical Operating Performance FIGURE 7. VOUT REGULATION vs LOAD 2.25MHz 1.5VOUT FIGURE 8. VOUT REGULATION vs LOAD 2.25MHz 1.8VOUT 2.55 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.54 5V VIN PFM 2.53 2.52 2.51 2.50 2.49 0.0 3.3V VIN PFM 3.3V VIN PWM 5V VIN PWM 3.42 3.40 3.38 3.36 3.34 3.32 3.30 0.0 5V VIN PFM 5V VIN PWM 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 9. VOUT REGULATION vs LOAD 2.25MHz 2.5VOUT FIGURE 10. VOUT REGULATION vs LOAD 2.25MHz 3.3VOUT 1.83 OUTPUT VOLTAGE (V) 1.82 1.81 1.80 1.79 1.78 1.77 2.0 0.4A LOAD PWM 0.8A LOAD PWM 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0A LOAD PWM 1.83 OUTPUT VOLTAGE (V) 1.82 1.81 1.80 1.79 1.78 1.77 2.0 0A LOAD 0.4A LOAD 0.8A LOAD 2.5 3.0 INPUT VOLTAGE (V) 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 FIGURE 11. OUTPUT VOLTAGE REGULATION vs VIN 1.8VOUT PWM MODE FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN 1.8VOUT PFM MODE 7 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 500ns/DIV LX1 2V/DIV 500ns/DIV LX2 2V/DIV Typical Operating Performance VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.5A/DIV IL2 0.5A/DIV FIGURE 13. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 (PWM) FIGURE 14. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (PWM) 500ns/DIV LX1 2V/DIV 500ns/DIV LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.5A/DIV IL2 0.5A/DIV FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 (PFM) FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (PFM) LX1 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV 500ns/DIV IL1 0.5A/DIV 500ns/DIV IL2 0.5A/DIV FIGURE 17. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1 FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2 8 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV Typical Operating Performance IL1 0.5A/DIV IL2 0.5A/DIV 50s/DIV 50s/DIV FIGURE 19. LOAD TRANSIENT CHANNEL 1 (PWM) FIGURE 20. LOAD TRANSIENT CHANNEL 2 (PWM) LX1 2V/DIV LX2 2V/DIV VOUT1 RIPPLE 50mV/DIV 50s/DIV IL1 0.5A/DIV 50s/DIV VOUT2 RIPPLE 50mV/DIV IL2 0.5A/DIV FIGURE 21. LOAD TRANSIENT CHANNEL 1 (PFM) FIGURE 22. LOAD TRANSIENT CHANNEL 2 (PFM) 50s/DIV 50s/DIV EN2 2V/DIV VOUT2 0.5V/DIV EN1 2V/DIV VOUT1 1V/DIV IL2 0.5A/DIV IL1 0.5A/DIV PG 5V/DIV PG 5V/DIV FIGURE 23. SOFT-START WITH NO LOAD CHANNEL 1 (PWM) FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 2 (PWM) 9 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 50s/DIV EN1 2V/DIV VOUT1 1V/DIV 50s/DIV Typical Operating Performance EN2 2V/DIV VOUT2 0.5V/DIV ILL 0.5A/DIV I 0.5A/DIV IL2 0.5A/DIV PG 5V/DIV PG 5V/DIV FIGURE 25. SOFT-START AT NO LOAD CHANNEL 1 (PFM) FIGURE 26. SOFT-START AT NO LOAD CHANNEL 2 (PFM) 50s/DIV EN1 2V/DIV 50s/DIV EN2 2V/DIV VOUT1 1V/DIV VOUT2 0.5V/DIV IL1 0.5A/DIV IL2 0.5A/DIV PG 5V/DIV PG 5V/DIV FIGURE 27. SOFT-START AT FULL LOAD CHANNEL 1 FIGURE 28. SOFT-START AT FULL LOAD CHANNEL 2 1ms/DIV EN1 5V/DIV EN2 5V/DIV 1ms/DIV VOUT2 0.5V/DIV VOUT1 1V/DIV IL1 0.5A/DIV IL2 0.5A/DIV PG 5V/DIV PG 5V/DIV FIGURE 29. SOFT-DISCHARGE SHUTDOWN CHANNEL 1 FIGURE 30. SOFT-DISCHARGE SHUTDOWN CHANNEL 2 10 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) 200ns/DIV LX1 2V/DIV LX1 2V/DIV 200ns/DIV Typical Operating Performance SYNCH 2V/DIV SYNCH 2V/DIV IL1 0.5A/DIV VOUT1 RIPPLE 20mV/DIV IL1 0.5A/DIV VOUT1 RIPPLE 20mV/DIV FIGURE 31. CH1 STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 4MHz FIGURE 32. CH1 STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 4MHz 200ns/DIV LX2 2V/DIV 200ns/DIV LX2 2V/DIV SYNCH 2V/DIV SYNCH 2V/DIV VOUT2 RIPPLE 20mV/DIV IL2 0.5A/DIV IL2 0.5A/DIV VOUT2 RIPPLE 20mV/DIV FIGURE 33. CH2 STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 4MHz FIGURE 34. CH2 STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 4MHz 100ns/DIV LX1 5V/DIV 100ns/DIV LX1 5V/DIV LX2 5V/DIV LX2 5V/DIV SYNCH 5V/DIV SYNCH 5V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV FIGURE 35. CH1 AND CH2 STEADY STATE OPERATION AT NO LOAD (PFM) WITH FREQUENCY = 4MHz FIGURE 36. CH1 AND CH2 STEADY STATE OPERATION AT FULL LOAD (PFM) WITH FREQUENCY = 4MHz 11 FN6858.1 April 29, 2010 ISL8088 (Unless otherwise noted) operating conditions are: TA = +25C, VIN = 2.75V to 5.5V, EN = VIN, L1 = L2 = 2.2H, C1 = 10F, C2 = C4 = 10F, VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1 = IOUT2 = 0A to 800mA. (Continued) PHASE1 5V/DIV LX1 5V/DIV Typical Operating Performance IL1 0.5A/DIV VOUT1 1V/DIV VOUT1 1V/DIV IL1 0.5A/DIV PG 5V/DIV 10s/DIV 500s/DIV PG 5V/DIV FIGURE 37. OUTPUT SHORT CIRCUIT CHANNEL 1 FIGURE 38. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 1 10s/DIV PHASE2 5V/DIV 500s/DIV LX2 5V/DIV VOUT2 0.5V/DIV IL2 0.5A/DIV IL2 0.5A/DIV VOUT2 1V/DIV PG 5V/DIV PG 5V/DIV FIGURE 39. OUTPUT SHORT CIRCUIT CHANNEL 2 FIGURE 40. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 2 2.4 VIN 6V IOUT1 OC OUTPUT CURRENT (A) 2.0 1.6 1.2 0.8 0.4 0 -50 VIN 3.5V IOUT2 OC VIN 6V IOUT2 OC VIN 3.5V IOUT1 OC -30 -10 10 20 50 70 90 110 TEMPERATURE (C) FIGURE 41. OUTPUT CURRENT LIMIT vs TEMPERATURE 12 FN6858.1 April 29, 2010 ISL8088 Block Diagram SHUTDOWN EN1 SOFTSTART + 27pF 200k + COMP - SHUTDOWN VIN PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER + CSA1 + OCP + SKIP 0.59V BANDGAP 0.6V + EAMP 3pF SLOPE COMP + + SCP - LX1 PGND FB1 1.6k 0.3V VIN 1M PG SGND + 0.552V - PG1 OSCILLATOR 0.09V ZERO-CROSS SENSING 1ms DELAY SYNC THERMAL SHUTDOWN SOFTSTART + 27pF 200k + COMP - SHUTDOWN SHUTDOWN EN2 SHUTDOWN VIN 3pF SLOPE COMP FB2 1.6k 0.3V SCP + + 0.552V 13 + - BANDGAP 0.6V EAMP PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER LX2 PGND + CSA2 + OCP + SKIP 0.59V + PG2 0.09V ZERO-CROSS SENSING FN6858.1 April 29, 2010 ISL8088 Theory of Operation The ISL8088 is a dual 800mA step-down switching regulator optimized for battery-powered or mobile applications. The regulator operates at 2.25MHz fixed switching frequency under heavy load conditions to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The two channels are in-phase operation. The quiescent current when the outputs are not loaded is typically only 30A. The supply current is typically only 6.5A when the regulator is shut down. The dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier CSA-output. The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage control loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately shortly. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 27pF and 200k RC network. The maximum EAMP voltage output is precisely clamped to 0.8V. VEAMP VCSA DUTY CYCLE IL PWM Control Scheme Pulling the SYNC pin LOW (<0.4V) forces the converter into PWM mode in the next switching cycle regardless of output current. Each of the channels of the ISL8088 employ the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting shown in the "Block Diagram" on page 13. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-Channel MOSFET when it is turned on and the current sense amplifier CSA1 (or CSA2 on Channel 2). The gain for the current sensing circuit is typically 0.285V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp-up. When the sum of the current amplifier CSA1 (or CSA2) and the compensation slope (0.33V/s) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and to turn on the N-Channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 42 shows the typical operating waveforms during the PWM operation. PWM VOUT FIGURE 42. PWM OPERATION WAVEFORMS SKIP Mode Pulling the SYNC pin HIGH (>2.0V) forces the converter into PFM mode. The ISL8088 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 43 illustrates the skip-mode operation. A zero-cross sensing circuit shown in the "Block Diagram" on page 13 monitors the N-MOSFET current for zero crossing. When 8 consecutive cycles of the N-MOSFET crossing zero are detected, the regulator enters the skip mode. During the 8 detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. PFM CLOCK 8 CYCLES IL 0 NOMINAL +1.5% VOUT NOMINAL PFM CURRENT LIMIT LOAD CURRENT FIGURE 43. SKIP MODE OPERATION WAVEFORMS 14 FN6858.1 April 29, 2010 ISL8088 Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in the "Block Diagram" on page 13. Each pulse cycle is still synchronized by the PWM clock. The P-MOSFET is turned on at the clock and turned off when its current reaches the threshold of 250mA. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above the nominal voltage, the P-MOSFET is turned off immediately. Then the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the clock, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. UVLO When the input voltage is below the undervoltage lock out (UVLO) threshold, the regulator is disabled. Enable The enable (EN1, EN2) input allows user to control the turning on or off the regulator for purposes such as power-up sequencing. The regulator is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft start-up begins. Soft-Start-Up The soft-start-up eliminates the in-rush current during the start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. In force PWM mode, the IC will continue to start-up in PFM mode to support pre-biased load applications. Synchronization Control The frequency of operation can be synchronized up to 4MHz by an external signal applied to the SYNC pin. The falling edge on the SYNC triggered the rising edge of the PWM ON pulse. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to GND through an internal 100 switch. Overcurrent Protection CSA1 and CSA2 is used to monitor output 1 and output 2 channels respectively. The overcurrent protection is realized by monitoring the CSA_ output with the OCP threshold logic, as shown in "Block Diagram" on page 13. The current sensing circuit has a gain of 0.285V/A, from the P-MOSFET current to the CSA_output. When the CSA_ output reaches the threshold of 590mV, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFETs. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Power MOSFETs The power MOSFETs are optimize for best efficiency. The ON-resistance for the P-MOSFET is typically 180m and the ON-resistance for the N-MOSFET is typical 180m. 100% Duty Cycle The ISL8088 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL8088 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET. PG The power-good signal, (PG) monitors both of the output channels. When powering up, the open-collector power-on-reset output holds low for about 1ms after VO1 and VO2 reaches the preset voltages. The PG output also serves as a 1ms delayed Power-Good signal. If one of the output is disabled, then PG only monitors the active channels. There is an internal 1M pull-up resistor. TABLE 1. PG EN1 0 0 1 1 EN2 0 1 0 1 PG1 PG2 INTERNAL INTERNAL X X 1 1 X 1 X 1 PG 0 1 1 1 Thermal Shut-Down The ISL8088 has built-in thermal protection. When the internal temperature reaches +150C, the regulator is completely shut down. As the temperature drops to +130C, the ISL8088 resumes operation by stepping through a soft-start-up. Applications Information Output Inductor and Capacitor Selection To consider steady state and transient operation, ISL8088 typically uses a 2.2H output inductor. Higher or lower inductor values can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V applications, in order to decrease the inductor current ripple and output voltage ripple, the 15 FN6858.1 April 29, 2010 ISL8088 output inductor value can be increased. The inductor ripple current can be expressed as shown in Equation 1: VO V O * 1 - --------- V IN I = -------------------------------------L * fS (EQ. 1) The output voltage programming resistor, R2 (or R5 in Channel 2), will depend on the desired output voltage of the regulator. The value for the feedback resistor is typically between 0 and 750k as shown in Equation 2. Let R3 = 100k, then R2 will be: V OUT R 2 = R 3 --------------- - 1 V FB (EQ. 2) The inductor's saturation current rating needs be at least larger than the peak current. The ISL8088 protects the typical peak current 1.2A. The saturation current needs be over 1.8A for maximum output current application. ISL8088 uses internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended minimum output capacitor values are shown in Table 2 for the ISL8088. TABLE 2. OUTPUT CAPACITOR VALUE vs VOUT ISL8088 VOUT (V) 0.8 1.2 1.6 1.8 2.5 3.3 3.6 COUT (F) 10 10 10 10 10 6.8 8.6 L (H) 1.0~2.2 1.0~2.2 1.0~2.2 1.5~3.3 1.5~3.3 1.5~4.7 1.5~4.7 If the output voltage desired is 0.6V, then R3 is left unpopulated and short R2. For faster response performance, add 47pF in parallel to R2. Input Capacitor Selection The main functions for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. One 10F X5R or X7R ceramic capacitor is a good starting point for the input capacitor selection for both channels. PCB Layout Recommendation The PCB layout is a very important converter design step to make sure the designed converter works well. For ISL8088, the power loop is composed of the output inductor (L's), the output capacitor (COUT1 and COUT2), the LX's pins, and the GND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the LX_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as closely as possible to the VIN pin. The ground of input and output capacitors should be connected as closely as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. In Table 2, the minimum output capacitor value is given for different output voltage to make sure the whole converter system is stable. Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to "Typical Application" on page 2. 16 FN6858.1 April 29, 2010 ISL8088 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 3/18/10 REVISION FN6858.1 CHANGE Page 13: Added inverter symbol in Block Diagram to PG OR Gate. Per new datasheet standard, moved: Pin Configuration from pg1 and Pin Desc table from pg 2, both to pg 3. Typ App diagram from pg 3 to pg 2 Initial release 9/21/09 FN6858.0 Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL8088 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6858.1 April 29, 2010 ISL8088 Package Outline Drawing L10.3x3C 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 2, 09/09 3.00 A B 10 6 PIN 1 INDEX AREA 1 2 3.00 2.38 0.50 6 PIN #1 INDEX AREA 10 x 0.25 6 (4X) 0.10 C B 1.64 TOP VIEW 10x 0.40 5 (4X) 0.10 M C B BOTTOM VIEW PACKAGE OUTLINE (10x 0.25) (10 x 0.60) SEE DETAIL "X" 0.10 C 0.90 MAX C BASE PLANE 2.38 0.20 SIDE VIEW SEATING PLANE 0.08 C (8x 0.50) 1.64 TYPICAL RECOMMENDED LAND PATTERN C 0.20 REF 0.05 DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be 5 2. 3. 4. either a mold or mark feature. 7. COMPLAINT TO JEDEC MO-229-WEED-3 except for E-PAD dimensions. 18 FN6858.1 April 29, 2010 |
Price & Availability of ISL808810
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |